At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking to hire an intern to join our Physical Verification / EDA engineering team. This internship will provide hands‑on experience working on real design and verification flows and collaborating closely with senior engineers.

Preferred Major:

• Electrical Engineering (EE) – primary
• Computer Engineering (CE) – secondary

The ideal candidate should meet the following requirements, listed in order of priority:

Understanding of ESD design concepts Familiarity with ESD protection structures, design considerations, and reliability fundamentals. Knowledge of SPICE formats Ability to read and understand SPICE netlists and basic simulation concepts. Ability to read Tcl code and write scripts to analyze results Comfortable reading existing Tcl procedures and writing small scripts to extract, post‑process, or summarize verification outputs/logs. Experience with EDA tools Exposure to common EDA tools used in IC design and physical verification. Familiarity with the PERC flow in Physical Verification tools Basic understanding of PERC concepts and rule‑based electrical checks.

This intern will work on practical engineering tasks related to design and physical verification flows, help debug real issues, and gain exposure to production‑level EDA methodologies.

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