招聘
必备技能
Python
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are looking for a Product Engineer to drive the development and customer adoption of Analog Design automation flows in Virtuoso, including AI Driven optimization, parasitic‑aware design, and layout‑driven design methodologies.
This is a customer‑facing role that sits at the intersection of analog circuit design, design automation technology, and customer design workflows, and plays a key role in scaling next‑generation analog design automation flows.
We are looking for highly motivated and self‑driven engineers with:
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Strong hands‑on experience in analog / mixed‑signal circuit design.
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Deep familiarity with Virtuoso schematic, simulation, and ADE environments.
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Exposure to design automation, circuit optimization, or migration flows.
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Understanding of layout‑dependent effects and parasitic impact on circuit performance.
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Proven ability to work directly with customers, understand real design challenges, and articulate technical concepts clearly.
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Scripting or automation experience (SKILL, Python, or equivalent) is a plus.
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BS/MS degree in Electrical/Computer Engineering (or related degree) with at least 5 years of relevant experience
The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
3.3
7条评价
工作生活平衡
2.0
薪酬
2.5
企业文化
1.8
职业发展
2.0
管理层
1.5
15%
推荐给朋友
优点
Built strong client relationships
Useful for repetitive tasks
Employment opportunities
缺点
Poor management and micromanagement
Lack of career growth opportunities
Technical architecture and code quality issues
薪资范围
65个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试经验
1次面试
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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