About the Role

Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like i Phones, i Pads, and Macs. We're seeking highly skilled Analog Layout engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering Ser Des, PLLs, and sensors.

As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will involve creating custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams.

This job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology. You want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products, challenging oneself, and broadening skillsets in a dynamic, innovative work culture!

Responsibilities

Analog Layout engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include:

• Crafting sophisticated layouts for mixed-signal and analog circuits
• Reviewing floorplans and analyzing intricate circuits with circuit designers
• Running complete sets of design verification tools
• Planning/scheduling work and coordinating vital layout tradeoffs
• Interpreting LVS, DRC, and ERC reports to find the fastest way to complete the layout, exceeding engineering specifications and expectations

Preferred Qualifications

• 10+ years of experience in analog/mixed-signal layout design, with a focus on deep submicron CMOS circuits and at least 3+ years in FinFET technologies
• Programming/scripting knowledge in SKILL, Perl, TCL, Shell, and/or Python
• Familiar with Machine Learning and AI concepts
• Proven expertise in implementing analog layout designs, achieving tight matching, low noise, and low power consumption
• Must recognize failure-prone circuit and layout structures, have experience with analog and DFM standards, and be able to identify the best approach to solving problems
• High proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly
• Technical understanding of IR drop, RC delay, electromigration, self-heating, and coupling capacitance
• High proficiency in interpreting physical verification reports (DRC, ERC, LVS, etc.)
• Experience using Cadence Virtuoso's advanced features (XL, EAD, APR, and Constraint Manager)
• Excellent communication skills and ability to work with cross-functional teams
• Cadence Innovus
• CAD Automation experience
• PCell creation experience
• MSEE or Ph.D. in Electrical and Computer Engineering

Minimum Qualifications

• BS and a minimum of 10 years relevant industry experience

Equal Opportunity

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.