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CPU ML Microarchitect/RTL Engineer

Apple

CPU ML Microarchitect/RTL Engineer

Apple

Santa Clara, CA

·

On-site

·

Full-time

·

1mo ago

Benefits & Perks

Health, dental, and vision coverage

Wellness benefits

Flexible PTO policy

Top Tier compensation with equity

Required Skills

Airflow

TensorFlow

Python

CPU ML Microarchitect/RTL Engineer

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!

About the Role

Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the i Phone, i Pad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer to drive CPU machine-learning accelerator architecture and RTL development for Apple Silicon.

Responsibilities

As a CPU ML Microarchitect/RTL Engineer, you will own or participate in the following:

  • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
  • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
  • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
  • Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
  • Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power

Minimum Qualifications

  • Minimum BS and 10+ years of relevant industry experience
  • Experience with microprocessor architecture
  • Experience with logic design principles with timing and power implications
  • Experience in Verilog or VHDL
  • Experience with simulators and waveform debugging process

Preferred Qualifications

  • Expertise in one or more of the following areas: out-of-order execution, instruction scheduling, integer and floating point execution, load/store execution, cache and memory subsystems
  • Understanding of low power microarchitecture techniques
  • Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
  • Experience in C or C++ programming
  • Experience using an interpretive language such as Perl or Python

Equal Opportunity

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

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About Apple

Apple

Apple

Public

A technology company that designs, manufactures, and markets consumer electronics, personal computers, and software.

10,001+

Employees

Cupertino

Headquarters

$3.5T

Valuation

Reviews

4.0

10 reviews

Work Life Balance

4.0

Compensation

4.2

Culture

3.8

Career

3.5

Management

3.2

75%

Recommend to a Friend

Pros

Great coworkers and people

Excellent benefits and perks

Fast-paced and engaging work environment

Cons

High expectations and pressure

Management quality varies

Limited career progression opportunities

Salary Ranges

17,968 data points

Junior/L3

L2

L3

L4

L5

L6

M3

M4

M5

M6

Principal/L7

Senior/L5

Staff/L6

Junior/L3 · Data Scientist ICT2

0 reports

$121,979

total / year

Base

-

Stock

-

Bonus

-

$103,682

$140,276

Interview Experience

5 interviews

Difficulty

3.4

/ 5

Duration

28-42 weeks

Offer Rate

20%

Experience

Positive 20%

Neutral 40%

Negative 40%

Interview Process

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Behavioral Interview

5

Onsite/Virtual Interviews

6

Team Matching

7

Offer

Common Questions

Coding/Algorithm

System Design

Behavioral/STAR

Technical Knowledge

Culture Fit