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Apple
RFIC Design Engineer
3 weeks ago• Irvine, CA
Viewed on February 1, 2026
Apply on company site
About Us
Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.
- Size: 10000+ employees
- Industry: Technology, Information Technology, Software, Consumer Goods & Services
View Company Profile:
Do you have a passion for invention and self-challenge. Do you thrive with pushing the limits of what's considered feasible? As part of an outstanding team, you'll craft sophisticated, groundbreaking projects that deliver more performance in our products than ever before. You'll work across fields to transform improved hardware elements into a coordinated design. Join us, and you'll help us innovate new technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you'll push the industry boundaries of what wireless systems can do and improve the product experience for our customers worldwide.
Description:
The wireless RFIC team architects, designs, and validates radio transceivers integrated into sophisticated wireless So Cs. Our wireless organization is responsible for all aspects of wireless silicon development that transform the user experience at the product level, all of which is driven by an outstanding vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering! As an engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group, chipping in to Apple's innovative wireless connectivity solutions into hundreds of millions of products.","responsibilities":"As an RFIC Design Engineer, you will be responsible for providing RFIC solutions for wireless SoC and driving them to mass production for Apple's Wireless Connectivity products. Responsibilities include:
Led design of radio transceiver chains, including TX, RX, and PLL-LOGen for wireless connectivity products.
Drive radio KPI (power, area, performance) to meet product requirements.
Work with multi-functional teams including platform architecture, wireless design, RF HW and SW to define radio features enabling wireless innovation.
Work closely with RF Systems in block level and high level specifications of the TX and RX line ups and PLL-LOGen, and accurate distribution of spec margins in the chain.
Hands-on design contributions, starting from concept, architecture, and topology to transistor-level feasibility studies and KPI trade-off analysis to actual design, simulations, and extractions.
Design of RF and Analog loopbacks for calibration and compensation.
Work through Co-Existence scenarios and design to meet the Co Ex requirements.
Be responsible for the floorplan layout and verification of the design to ensure a successful tape-out.
Close collaboration with RFIC test engineers in the bring up, debug and optimization of the wireless connectivity chip through the productization.
Provide design versus silicon measurements correlation and compliance with specifications for volume production.
Preferred Qualifications:
MSEE and PhD plus relevant industry experience.
Solid Understanding of the impact of modulation type on radio architecture and requirements.
Validated capability to work with digital design group for an optimum partition between digital and analog domains.
Familiarity with the integration flows and challenges of wireless SoC's.
Good understanding of desense and can work with board RF/HW/Antenna teams to optimize board/module layouts for desense mitigation.
Familiarity with mixed-signal mode verification methodology (System Verilog, AMS, Nanotime).
Extensive experience in Silicon characterization and debugging.
Ability to drive strong production test/QA methodologies.
Minimum Qualifications:
BS and 10+ years of relevant industry experience.
Shown RF/analog and mixed-signal design experience in groundbreaking RF CMOS design.
Strong understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability, and other analog impairments.
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By signing up, you agree to our Experience in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS), and similar tools.
Direct experience in designing and bringing wireless transceivers into mass production in deep sub-micron RFCMOS technology.
Experience should also include understanding DFT and DFM techniques for mass production environments.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Client-provided location(s): Irvine, CAJob ID: apple-200623902-3543_rxr-660Employment Type: OTHERPosted: 2026-01-07T19:12:53Apply on company site
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RFIC Design Engineer Apple Irvine, CARFIC Design Engineer Apple San Diego, CARFIC Design Engineer Apple Irvine, CA
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About Apple

Apple
PublicA technology company that designs, manufactures, and markets consumer electronics, personal computers, and software.
10,001+
Employees
Cupertino
Headquarters
$3.5T
Valuation
Reviews
4.0
10 reviews
Work Life Balance
4.0
Compensation
4.2
Culture
3.8
Career
3.5
Management
3.2
75%
Recommend to a Friend
Pros
Great coworkers and people
Excellent benefits and perks
Fast-paced and engaging work environment
Cons
High expectations and pressure
Management quality varies
Limited career progression opportunities
Salary Ranges
17,968 data points
L2
L3
L4
L5
L6
L2 · Business Analyst L2
0 reports
$114,215
total / year
Base
$45,686
Stock
$57,108
Bonus
$11,422
$79,951
$148,480
Interview Experience
5 interviews
Difficulty
3.4
/ 5
Duration
28-42 weeks
Offer Rate
20%
Experience
Positive 20%
Neutral 40%
Negative 40%
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Behavioral Interview
5
Onsite/Virtual Interviews
6
Team Matching
7
Offer
Common Questions
Coding/Algorithm
System Design
Behavioral/STAR
Technical Knowledge
Culture Fit
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