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RFIC Layout Engineer

Apple

RFIC Layout Engineer

Apple

Alice, TX

·

On-site

·

Full-time

·

1mo ago

Benefits & Perks

Competitive salary and equity package

Comprehensive health, dental, and vision insurance

Parental leave

Flexible work arrangements

Professional development budget

Generous paid time off and holidays

Equity

Healthcare

Parental Leave

Flexible Hours

Learning

Required Skills

TypeScript

React

Python

RFIC Layout Engineer

3 weeks ago• Alice, TX
Apply on company site

About Us

Working at Apple means doing more than you ever thought possible and having more impact than you ever imagined.
Size: 10000+ employees

Industry: Technology, Information Technology, Software, Consumer Goods & Services

The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and band gap references.

Description:

As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes.","responsibilities":"Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.

Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking.

Co-work with designers on block level floorplanning.

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Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.

Preferred Qualifications:

Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.

Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.

Solid understanding of RC delay, electromigration, and coupling.

Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE.

High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in Fin Fet Technology.

Knowledge of CADENCE layout tools.

Excellent communication skills.

Scripting skills in PERL or SKILL.

Minimum Qualifications:

BS and 10+ years of relevant industry experience.

Fin Fet experience.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Client-provided location(s): Alice, TX

Job ID: apple-200630234-1756_rxr-660

Employment Type: OTHER

Posted: 2026-01-07T19:12:55
Apply on company site

Perks and Benefits

Health and Wellness

Parental Benefits

Work Flexibility

Office Life and Perks

Vacation and Time Off

Financial and Retirement

Professional Development

Diversity and Inclusion

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About Apple

Apple

Apple

Public

A technology company that designs, manufactures, and markets consumer electronics, personal computers, and software.

10,001+

Employees

Cupertino

Headquarters

$3.5T

Valuation

Reviews

4.0

10 reviews

Work Life Balance

4.0

Compensation

4.2

Culture

3.8

Career

3.5

Management

3.2

75%

Recommend to a Friend

Pros

Great coworkers and people

Excellent benefits and perks

Fast-paced and engaging work environment

Cons

High expectations and pressure

Management quality varies

Limited career progression opportunities

Salary Ranges

17,968 data points

L2

L3

L4

L5

L6

M3

M4

M5

M6

L2 · Industrial Designer L2

0 reports

$320,450

total / year

Base

$128,180

Stock

$160,225

Bonus

$32,045

$224,315

$416,585

Interview Experience

5 interviews

Difficulty

3.4

/ 5

Duration

28-42 weeks

Offer Rate

20%

Experience

Positive 20%

Neutral 40%

Negative 40%

Interview Process

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Behavioral Interview

5

Onsite/Virtual Interviews

6

Team Matching

7

Offer

Common Questions

Coding/Algorithm

System Design

Behavioral/STAR

Technical Knowledge

Culture Fit