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Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the i Phone, i Pad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer who can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.

Description:

As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following:

• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification

• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals

• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification

• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance

• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power

Preferred Qualifications:

Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction

Understanding of low power microarchitecture techniques

Understanding of high-performance techniques and trade-offs in a CPU microarchitecture

Experience in C or C++ programming

Experience using an interpretive language such as Perl or Python

Minimum Qualifications:

Minimum BS and 10+ years of relevant industry experience

Experience with microprocessor architecture

Experience with logic design principles with timing and power implications

Experience in Verilog or VHDL:

Experience with simulators and waveform debugging process

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Pay & Benefits:

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.