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In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.

Description

As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project.

Responsibilities include but are not limited to:

• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency.

• Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.

Preferred Qualifications

Prior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs

Experience in a static timing analysis tool such as Prime Time®/Tempus®

Knowledge of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, and logic equivalence

Understanding of deep sub-micron technologies and scaling trends

Working knowledge of CPU microarchitecture

Possess data parsing, analysis and representation/plotting skills

Minimum Qualifications

Minimum BS and 3+ years of relevant experience

Experience with static timing analysis, noise analysis, and fixing noise in designs

Experience with variation modeling

Experience with TCL and either Perl or Python:

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

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Client-provided location(s): Santa Clara, CA

Job ID: apple-200628441-3760_rxr-660

Employment Type: OTHER

Posted: 2026-01-07T19:12:54
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