Jobs
Benefits & Perks
•Healthcare
•401(k)
•Paid vacation
•Flexible Hours
•Healthcare
•401k
•Flexible Hours
Required Skills
Verilog
SystemVerilog
Digital design
ASIC design
SoC design
RTL coding
Timing analysis
Design verification
Low power design
DFT
About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).
Staff Digital Design Engineer
Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare.
ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.
ADI At A Glance
Analog Devices operates at the center of the modern digital economy, converting real-world phenomena into actionable insight with its comprehensive suite of analog and mixed signal, power management, radio frequency (RF), and digital and sensor technologies. ADI serves 125,000 customers worldwide with more than 75,000 products in the industrial, communications, automotive, and consumer markets. ADI is headquartered in Wilmington, MA. Visit http://www.analog.com.
Description:
The Digital IP team within Analog Devices Inc. is responsible for developing, curating, and providing reusable strategic IPs to Business Units to accelerate product development across the company. The team is looking for an experienced Digital Design Lead who will be responsible for providing technical leadership to the digital design team, while managing IP development and delivery.
The ideal candidate would be someone with strong technical background combined with management acumen and demonstrable ability to handle ambiguity while still finding creative ways to make things happen.
A key focus area for this position includes interacting and engaging with internal customers to communicate, identify, improve, and maintain developed IP, as well as scout for 3rd party IPs and evaluate them on a regular basis for future requirements.
Job Responsibilities:
- Provide technical leadership and mentorship to digital design engineers across CDC, low‑power design, synthesis and timing closure, DFT improvements, and silicon debug
- Architect and design key digital blocks (accelerators, datapath IPs) in Verilog/System Verilog with configurability to optimize Power, Performance, and Area (PPA)
- Demonstrate deep understanding of heterogeneous processor subsystems (A55, M55, M4, U55, RISC‑V, DSP) and supporting infrastructure including caches, interconnects, GIC, DMA, MMU, Core Sight debug/trace, TZC, SMPU, and SPU
- Collaborate closely with product teams, program managers, and leadership to align schedules, milestones, commitments, and deliverables
- Drive adoption of AI tools (e.g., Copilot and approved third‑party tools) to improve efficiency and accelerate execution
- Build and lead expertise in complex interfaces and protocols including DDR, Ethernet, eMMC/SD, MIPI, Display Port, HDMI, PCIe, and high‑speed D2D
- Drive development of IP‑centric design management infrastructure and flows across Methodics, Perforce, GitHub, and IP catalog systems
- Develop and maintain a digital IP catalog to enable efficient information sharing and reuse across business units
- Package digital IPs for seamless integration across design stages, including RTL, constraints, CDC and timing waivers, DFT DRCs/waivers, and software programming sequences
- Conduct detailed design reviews and enforce adherence to quality metrics and best practices
- Lead evaluation of third‑party IPs on PPA, design quality, DFT robustness, DV maturity, and integration ease; provide clear recommendations
- Establish consistent benchmarking and evaluation flows for in‑house and third‑party IPs
- Manage and streamline consolidation and curation of digital IP assets, including standard peripherals, processor cores, and high‑speed interface IPs
- Reduce complexity and ambiguity across teams and processes by distilling technical detail into clear, actionable guidance and recommendations
Position Requirements:
-
Minimum B.E. /B. Tech degree in Electrical/Electronics/Computer science
-
12+ years of relevant experience with a strong focus on definition/ architecture/ u-arch/ design and hands-on RTL coding experience using Verilog and System-Verilog
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Strong understanding of all aspects of ASIC/SoC product development incl Design Verification/ timing constraints/ closure, physical implementation, quality assurance flows with hands-on prior experience in a few of these aspects
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Proven experience in managing/ handling large complex hardware projects in lead role
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Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions
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Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality
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Strong knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis, low power design
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Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis
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Ability to technically mentor a large digital design team
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Good interpersonal, teamwork and communication skills to drive discussions logically & effectively with teams spread geographically
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Strong understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols
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Knowledge of Processor/SoC architecture and/or DSP fundamentals
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Serve as the focal point for communications. Compile regular status updates for all stakeholders and effectively escalate critical issues and risks as necessary
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For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
Department of Commerce:
- Bureau of Industry and Security and/or the U.S.
Department of State:
- Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
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About Analog Devices

Analog Devices (NYSE: ADI) defines innovation and excellence in signal processing. ADI's analog, mixed-signal, and digital signal processing (DSP) integrated circuits (IC) play a fundamental role in converting, conditioning, and processing real-world phenomena such as light, sound, temperature, motion, and pressure into electrical signals to be used in a wide array of electronic equipment.
10,001+
Employees
Norwood
Headquarters
$95B
Valuation
Reviews
2.8
10 reviews
Work Life Balance
2.0
Compensation
3.5
Culture
2.5
Career
3.0
Management
1.8
35%
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Pros
Good pay and compensation
Interesting technology and smart people
Good benefits and stock options
Cons
Poor management and leadership
Bad work-life balance and overwork
High stress environment
Salary Ranges
698 data points
L6
Staff/L6
L6 ·
0 reports
$152,500
total / year
Base
-
Stock
-
Bonus
-
$129,625
$175,375
Interview Experience
4 interviews
Difficulty
3.5
/ 5
Duration
14-28 weeks
Experience
Positive 25%
Neutral 75%
Negative 0%
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Technical Interview Rounds
5
Hiring Manager Interview
6
Final Round/Decision
Common Questions
Technical Knowledge
Coding/Algorithm
System Design
Past Experience
Behavioral/STAR
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