About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

The Position

Analog Devices is seeking a senior digital design engineer for its Data Center & Energy (DCE) group. Within DCE, we deliver high‑reliability power, connectivity, and analytics solutions for modern data centers and energy infrastructure.

The successful candidate will implement and verify digital logic for mixed-signal So Cs that enable signal measurement and analytics. This role focuses on RTL development, verification, and integration, working closely with senior engineers and cross-functional teams to deliver robust, manufacturable solutions.

This is a demanding multi-disciplinary position with unique growth potential. The group culture aims to foster a challenging, exciting, and supportive environment. The team members must be comfortable working on a wide variety of products and technologies in a fast-paced and agile environment. Analog Devices rewards performance, innovation, and collaboration.

Responsibilities include, but are not limited to:

• Develop and verify RTL for digital blocks and subsystems; ensure functional correctness and timing closure

• Perform synthesis, static timing analysis, and support design-for-test (DFT) insertion and pattern generation

• Collaborate with analog, firmware, and validation teams to integrate digital content into mixed-signal So Cs

• Assist with silicon bring-up and debug; support lab measurements and correlation to simulation

• Contribute to methodology improvements and automation initiatives

Minimum Qualifications:

• BS in Electrical or Computer Engineering (or equivalent)

• 3+ years of experience in ASIC/SoC digital design

• Proficiency in Verilog/System Verilog and scripting languages (Python, C)

• Familiarity with RTL-to-GDS flows (e.g., Genus, Innovus, Tempus, Conformal)

• Understanding of DFT concepts and basic test strategies

• Working knowledge of analog circuit operation and lab practices

• Strong problem-solving skills and ability to work independently with minimal supervision

• Good organization; written and verbal communication skills

Preferred Qualifications:

• MS in Electrical or Computer Engineering (or equivalent)

• Experience with FPGA prototyping and system-level modeling

• Familiarity with power system components (VRMs, IBCs, BMCs) and board-level sequencing

• Exposure to standard interfaces and bus protocols (AMBA, I²C, SPI)

• Interest in methodology improvements and automation

• For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.

Department of Commerce:

• Bureau of Industry and Security and/or the U.S.

Department of State:

• Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days