About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

Staff Physical Design Engineer – eFPGA IPLocation:

San Jose, CA/ Austin,TX (Hybrid)Employment Type: Full-Time

About the Role

We are seeking a Staff Physical Design Engineer to join our embedded FPGA (eFPGA) IP implementation team. In this role, you will lead the physical design, timing closure, and sign-off for complex, hierarchical eFPGA fabrics implemented on advanced technology nodes.

You will work extensively with Cadence digital implementation tools and Siemens Calibre to ensure robust, high-quality, silicon-proven IP.

Key Responsibilities

• Execute Custompower grid planning, Custom Floorplanning , EM/IR analysis, and coordinate with power and packaging teams for full-chip integration.
• Own end-to-end Hierarchical physical implementation of eFPGA IP blocks — including fabric tiles, interconnect networks, and control logic.
• Drive all major phases of the RTL-to-GDSII flow using Cadence Genus, Innovus, Tempus, and Voltus.
• Perform detailed placement, CTS, routing, and optimization for timing, power, and area closure.
• Conduct clock-tree synthesis and multi-corner multi-mode (MCMM) timing analysis to achieve sign-off quality convergence.
• Automate design flows and develop Tcl/Python scripts to enhance PnR efficiency and reproducibility.
• Perform final sign-off analysis:Tempus for STA and ECO closure
• Voltus for power/IR verification
• Calibre for DRC/LVS and physical verification
• Collaborate closely with RTL, architecture, and CAD methodology teams to optimize design quality and flow robustness.
• Support post-silicon correlation and continuous improvement of physical implementation flows.

Required Qualifications

• B.S./M.S. in Electrical or Computer Engineering with 8+ years of experience in physical design.
• Expert proficiency with Cadence tools:Genus – synthesis and constraint management
• Innovus – floorplanning, placement, CTS, routing, and optimization
• Tempus – timing analysis and closure
• Voltus – power and EM/IR verification
• Hands-on experience at 16nm/7 nm/5 nm or lower nodes, including hierarchical and multi-voltage design.
• Strong understanding of UPF-based low-power flows,MCMM analysis, and timing sign-off.
• Skilled in Tcl and Python scripting for automation and tool integration.
• Proven track record of driving IP-level RTL-to-GDSII implementation with tight PPA targets.
• Experience with Calibre DRC/LVS for foundry sign-off.

Preferred Qualifications

• Background in FPGA/eFPGA architecture, routing fabrics, or programmable logic optimization is a Plus

• Experience with timing model generation,hierarchical design abstraction, and SoC IP integration.

• Exposure to flow development, CAD automation, or methodology ownership is a plus.

• For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.

Department of Commerce:

• Bureau of Industry and Security and/or the U.S.

Department of State:

• Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

The expected wage range for a new hire into this position is $154,841 to $232,261.-
Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

• This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.

• This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.