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Back Senior Staff Hardware Development Engineer (Package Design)JOB_DESCRIPTION.SHARE.HTMLCAROUSEL_PARAGRAPHJOB_DESCRIPTION.SHARE.HTMLPenang, Malaysia Engineering76585mail_outline Get future jobs matching this search Loginor Register Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package group, you will work across chip, technology and systems teams to define cost effective and high performance solutions. THE PERSON:This is a high visibility position working on multiple package families for the FPGA devices. The ideal candidate should have the ability to understand electrical requirements and translate to the proper package technology requirements that is cost effective and manufacturable. This role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages. KEY RESPONSIBILITIES:Use Cadence tools for design, modeling and simulations. Enable timely closure of designs by getting involved with pre-design negotiations with chip/system teams and take it to design sign off Use analytical and simulation tools to define package/module design requirements (technology, stackup etc) in the project conception stages and negotiate with chip/system teams on product specification Conduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stackup, manufacturing time etc) for various device packaging. Collaborate with PCB Layout Engineers to optimize the package ballmap and chip team to optimize the die size Develop multi-signal package/module models over 50 GHz bandwidth and suitable test structures for model to measurement correlation. Come up with performance metrics for organic package technologies in order to design high speed chips and systems Performing Power Integrity analysis for core as well as IO and generate power delivery network requirements with emphasis on model to measurement correlation Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations. PREFERRED EXPERIENCE:Have a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines Package/PCB layout experience. Experience in high power, Gbs IO products is a plus.
Current working Knowledge of Cadence package design tool is a must. knowledge of SKILL is a plus.
Working knowledge of 2D/3D package design and mod
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About AMD

AMD
PublicA semiconductor company that designs and develops graphics units, processors, and media solutions
10,001+
Employees
Santa Clara
Headquarters
Reviews
3.5
25 reviews
Work Life Balance
3.2
Compensation
4.1
Culture
3.6
Career
3.4
Management
3.1
65%
Recommend to a Friend
Pros
Good compensation and benefits
Positive work environment
Great management and coworkers
Cons
Poor work life balance
Micromanagement and excessive tracking
Too much pressure and workload
Salary Ranges
6 data points
L2
L3
L4
L5
L6
L2 · Data Analyst L2
0 reports
$76,430
total / year
Base
$30,572
Stock
$38,215
Bonus
$7,643
$53,501
$99,359
Interview Experience
5 interviews
Difficulty
3.6
/ 5
Duration
14-28 weeks
Offer Rate
60%
Experience
Positive 20%
Neutral 20%
Negative 60%
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Technical Interview
5
Hiring Manager Interview
6
Offer
Common Questions
Coding/Algorithm
Technical Knowledge
Behavioral/STAR
Past Experience
System Design
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