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SOC full chip physical verification Engineer

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• JOB_DESCRIPTION.SHARE.HTML
• Hyderabad, India
• Engineering
• 76009

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Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

MTS SILICON DESIGN ENGINEER:

THE ROLE:

The focus of this role is to lead full chip integration and physical verification activities. To actively work on automation of the integration activities thus reducing the human error. To improve the overall efficiency of the team by innovating and executing with leading EDA features.

THE PERSON:

Master’s/Bachelor’s Degree in Electrical/Electronic engineering with 10+ years of experience in FPGA/SOC full chip physical verification, PDK updates, bump/ubump layout is required. Strong scripting skills in PERL/TCL/Python is must.

Successful candidate would be responsible for full chip integration and physical verification of 7nm and lower nodes. You will be actively working with CAD and EDA vendors to improve and automate the integration flows thus by improving the overall functional efficiency. This job requires excellent teamwork, great communication and strong problem-solving skill.

KEY RESPONSIBILITIES:

• Full chip integration and physical verification of FPGA/SOC designs
• Work closely with PD, CAD, Si Tech, EMIR, PKG and EDA vendors for seamless integration of IPs into full chip for ontime tapeout.
• Actively work on automation of integration flows to improve the functional efficiency.
• Debug the full chip LVS/DRC/Antenna issues with multi point approach and ability to modify the rule files for quicker debug

PREFERRED EXPERIENCE:

• Should be well versed with Fin Fet technology DRC debugging and fixes.
• Experience in bump & ubump layouts and 3D integration of AoA or SSIT designs will be desirable.
• Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks.
• Knowledge of scripting languages like SKILL, PERL, TCL etc. is must.
• Strong problem solving skills and excellent communication skills.
• Sound knowledge of hierarchical layout handling including macros and full chip.
• Knowledge in PDK (DRC/LVS rule files) is preferred.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.
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