WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems.

Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary.

When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.

Join us as we shape the future of AI and beyond.

Together, we advance your career. THE TEAM: The Graphics Core IP hardware development organization is more than 1,000 engineers spread across multiple different geographies.

There are several subsystem development teams, system level verification teams, physical design team as well as a graphics IP specific project management team.

The Unified Translation Cache:

Level: 2 team is part of the Cache Memory Management Subsystem within Graphics organization and consists of engineers across different levels of experience.

The team is primarily based in Markham and emphasizes honesty, integrity, and teamwork.

We work closely with each other to deliver high quality design and achieve our team's goals and milestones across all of AMD's programs. THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.     THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general.

You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones.

You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE:  Multiple years of hands-on work experience developing block verification testbenches, developing test plans for a HW design, executing test verification of such HW, defining functional coverage, and delivering 100% functionally covered validated HW design.

Hands-on proven verification experience using languages such as System Verilog & UVM, and debugging simulation waveforms to root cause differences between test bench and hardware designs.

Proficient in debugging firmware and RTL code using simulation tools  Experienced with Verilog, System Verilog, C, and C++   Automating workflows in a distributed compute environment.

Strong background in the C++ language, preferably on Linux with exposure to Windows platform Scripting language experience: Perl, Ruby, Python, Makefile, shell preferred.

Experience: in Verification of Cache Subsystems

Preferred ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

# Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.
THE TEAM: The Graphics Core IP hardware development organization is more than 1,000 engineers spread across multiple different geographies.

There are several subsystem development teams, system level verification teams, physical design team as well as a graphics IP specific project management team.

The Unified Translation Cache:

Level: 2 team is part of the Cache Memory Management Subsystem within Graphics organization and consists of engineers across different levels of experience.

The team is primarily based in Markham and emphasizes honesty, integrity, and teamwork.

We work closely with each other to deliver high quality design and achieve our team's goals and milestones across all of AMD's programs. THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.     THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general.

You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones.

You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE:  Multiple years of hands-on work experience developing block verification testbenches, developing test plans for a HW design, executing test verification of such HW, defining functional coverage, and delivering 100% functionally covered validated HW design.

Hands-on proven verification experience using languages such as System Verilog & UVM, and debugging simulation waveforms to root cause differences between test bench and hardware designs.

Proficient in debugging firmware and RTL code using simulation tools  Experienced with Verilog, System Verilog, C, and C++   Automating workflows in a distributed compute environment.

Strong background in the C++ language, preferably on Linux with exposure to Windows platform Scripting language experience: Perl, Ruby, Python, Makefile, shell preferred.

Experience: in Verification of Cache Subsystems

Preferred ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.