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Back Senior Design Verification Engineer – Ser Des IPJOB_DESCRIPTION.SHARE.HTMLCAROUSEL_PARAGRAPHJOB_DESCRIPTION.SHARE.HTMLBangalore, India Engineering76590mail_outline Get future jobs matching this search Loginor Register Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.   THE ROLEWe are looking for a Senior Design Verification Engineer to join our Ser Des IP team focused on high-speed wireline transceivers (e.g., PAM4 at 56G/112G and beyond). In this role, you will verify complex Ser Des digital and mixed-signal-adjacent subsystems including adaptation/calibration loops, control state machines, datapath DSP blocks, and firmware-configurable features using System Verilog/UVM and robust reference modeling.

You will work closely with architecture, design, circuit/modeling, and validation teams to ensure correctness, coverage, and high confidence across PVT, jitter/noise stress conditions, and protocol/feature configurations. THE PERSONYou enjoy verifying systems where behavior emerges from algorithms + state + timing (not just combinational logic shows up in waveforms). You can translate high-level requirements into a rigorous test plan, build testbench infrastructure that scales, and debug issues with a structured approach using waveforms, logs, assertions, coverage, and model correlation.

You communicate clearly, handle ambiguity by asking the right questions, and drive closure by aligning design intent, models, and verification.KEY RESPONSIBILITIESOwn verification of Ser Des digital IP blocks such as:DSP datapath blocks (FFE/DFE/filtering, slicing/decoding, saturation/rounding)Control loops and adaptation logic (CDR/MM-like updates, EQ adaptation, calibration flows)ADC interface logic and calibration support (gain/offset/deskew control, monitoring hooks)Clocking/control interfaces and configuration registers Develop verification plans with clear coverage goals:Feature/config coverage, corner-case stimulus, error injection, reset/power-state coverage Build and maintain UVM environments:Agents, drivers, monitors, sequences, scoreboards, reference models Transaction-level logging and debug infrastructure for fast root-cause Create realistic stimulus:PRBS patterns, framed streams, randomized bursty traffic, backpressure Jitter/noise/error injection at the digital interface level (as supported by models)Drive verification closure using:Functional coverage, assertion-based checks, scoreboarding/model checking Regression triage and failure minimization Support simulation acceleration and emulation where applicable:Runtime optimization, stable builds, reproducible debug flows Collaborate cross-functionally with modeling, circuit, and firmware teams:Align RTL behavior to architectural intent and