WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.THE ROLE:
We are seeking an engineer with strong hands-on experience in FPGA build flows, design qualification, and developing infrastructure for platform regressions. This role is focused on developing robust smoke tests, functional test cases, and qualification workloads used to validate both FPGA designs and the associated platform software/toolchain flows.

THE PERSON: The successful candidate will architect and implement daily and nightly regression pipelines, integrate them into a unified infrastructure, and ensure continuous quality and reliability of FPGA based platform design flows at scale. This role sits at the intersection of FPGA engineering, software automation, and infrastructure-level validation.

• KEY RESPONSIBILITIES:

FPGA Design & Build Flow:

• Own FPGA compile/build flows (synthesis, place & route, timing closure, bitstream generation).

• Develop and maintain reference FPGA designs for build flow validation.

• Diagnose issues across RTL, constraints, tools, and platform dependencies.

• Platform Qualification & Toolchain Validation

• Develop targeted test cases for FPGA build flows, toolchain stability, and edge cases.

• Build scripts and automation for software stack validation (drivers, runtimes, APIs).

• Validate tool and environment changes, partner with vendors and internal teams on root cause and fixes.

• Define scalable design qualification criteria and coverage.

• Regression Infrastructure

• Design and maintain automated daily/nightly regression systems for FPGA and software toolchain validation.

• Enable distributed, scalable runs across on-prem or cloud resources.

• Automate result collection, triage, and failure classification.

• Infrastructure & CI/CD Integration

• Integrate FPGA regressions into the unified infrastructure and CI/CD pipelines.

• Interface with shared services (e.g., build orchestration, monitoring, logging).

• Enable standardized reporting, dashboards, and notifications for regression health.

PREFERRED EXPERIENCE:

• Large-scale FPGA farm or datacenter-style validation.

• Monitoring/logging tools (e.g., Grafana, Prometheus, ELK).

• Operating unified build/validation infrastructures across multiple teams.

• Hardware bring-up or silicon pre-/post-silicon validation.

• Cross-functional and geographically distributed team collaboration.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: San Jose, CA

This role is not eligible for Visa sponsorship

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.