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Back IP Design EngineerJOB_DESCRIPTION.SHARE.HTMLCAROUSEL_PARAGRAPHJOB_DESCRIPTION.SHARE.HTMLSan Jose, California Engineering77035USD $159,840.00/Yr.USD $239,760.00/Yr.mail_outline Get future jobs matching this search Loginor Register Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.   THE ROLE: We are looking for a self-motivated senior design engineer to be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. As a key contributor, you will focus on RTL design and validation of high-speed interfaces such as chip-to-chip interconnect, both on system and on package, and highly configurable mufti-protocol PHYs. Continuous technical innovation to increase productivity, to heighten quality of results, and to foster career development is integral to the role.   THE PERSON:  You demonstrate a strong passion for digital design, are a collaborative team player, and possess excellent analytical and problem-solving skills. You are eager to learn and take full ownership of challenges.  KEY RESPONSIBILITIES:  Perform RTL design of the digital components.

Experience with designing IPs for FPGAs (AMD/Altera).Good knowledge of FPGA tool chains (Vivado/Quartus).Develop and validate timing constraints involving multiple clock domains while working with physical design to harden IP.Help lead and mentor other engineers to achieve project goals and organizational growth.

Work with a functional (design) verification team to meet coverage and quality standards.

Analyze/fix Lint and CDC/RDC errors of the components.

Guarantee quality/timely deliverables meeting project’s schedule.

Help to improve and automate design process.

Support post-silicon product bring-up/debug.  PREFERRED EXPERIENCE:  Strong experience in designing digital components for high performance, low power SOC/FPGA.Design of digital circuits and components using Verilog/System Verilog Creating and maintenance of timing constraints for complex multi-clock designs.

Debugging in digital and mixed-signal simulation environment.

Power-optimization of digital designs.

Multi-clock domain designs.

Experience/Knowledge of DDR Memory Controllers and Calibration algorithms is a plus.

Logic synthesis, timing closure, logical equivalence checking and ECOs.

Scripting languages such as Perl, Tcl, or Python.

Collaboration with verification team.

Excellent verbal and interpersonal communication skills.

Excellent technical communications. Ability to produce technical documentation.

Exhibit strong ownership of tasks and responsibilities.   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in Electrical Engineering with relevant industry experience LOCATION:San Jose  This role is not el