WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.

About the Department:

Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices across North America and Asia. The team is responsible for developing and supporting DFX methodologies and automation tools for AMD’s cutting-edge APU, GPU, and game console products.

THE ROLE: As an Engineering Manager for the CDFX Design Verification team, you will lead a group of skilled verification engineers focused on developing and carrying out verification strategies for AMD’s DFT IP. This role involves team leadership, ensuring project delivery, providing technical guidance, and facilitating cross-functional coordination. The ultimate goal is to achieve first-pass silicon success for AMD’s next-generation CPUs, GPUs, and APUs.

THE PERSON: You are a technically strong engineer who thrives in a fast-paced environment and enjoys solving complex verification challenges. You take initiative, work independently, and influence others through your expertise and collaboration. You are passionate about delivering high-quality designs and improving productization efficiency across AMD’s portfolio.

KEY RESPONSIBILITIES:

• Lead and manage a team of design verification engineers by providing technical direction, mentorship, and performance feedback to support professional development and achieve project goals.
• Define and drive the verification strategy for DFT IP, ensuring all efforts are closely aligned with architectural objectives, project schedules, and established quality targets.
• Oversee the creation, review, and execution of test plans for both block-level and system-level verification to ensure comprehensive test coverage and reliable results.
• Ensure both functional and code coverage closure by tracking and reporting verification quality metrics for all deliverables.
• Collaborate effectively with design, architecture, and performance engineering teams to resolve complex technical challenges and optimize verification methodologies.
• Prioritize and allocate resources across various verification tasks and projects, maintaining an appropriate balance between execution speed and product quality.
• Champion improvements in verification methodology, lead automation initiatives, and promote best practices throughout the team.
• Support post-silicon debug efforts by assisting in the recreation and root-cause analysis of issues found in the lab or reported by customers.
• Represent the verification team during project reviews, planning meetings, and executive updates, ensuring clear communication of progress and challenges.

PREFERRED EXPERIENCE:

• Proven track record of leading ASIC or SoC design verification teams through successful product tape-outs and experience in a Management or Technical Leadership role.
• Strong expertise in System Verilog, UVM, and coverage-driven verification methodologies.
• Deep understanding of computer architecture and digital logic design
• Hands-on experience with EDA tools (Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Excellent debugging and problem-solving skills for complex, multi-clock domain designs.
• Scripting proficiency in Python, Perl, or similar for automation and regression management.
• Strong people management and communication skills to lead geographically distributed teams. This includes experience working with multi-site, cross-functional teams in a fast-paced semiconductor environment.
• Familiarity with formal verification and emulation/prototyping flows is a plus.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, or a related field preferred

LOCATION: Markham, ON

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.