HCL Technologies
Senior Test Lead - Design Validation
RoleQA
LevelSenior
LocationBangalore, India
WorkOn-site
TypeFull-time
Posted1 week ago
About the role
Job Summary
Verification engineer for DV So
C - TVP:
Key Responsibilities
Development and maintenance of UVM testbenches, including agents, sequences, scoreboards, monitors, and checkers
Skill Requirements
- ASIC IP-level verification using System Verilog and UVM testbench
development and maintenance - Test planning, execution, and closure at IP level
- Writing and debugging constraint-random tests
- Development and analysis of functional coverage and code coverage
- Strong Debugging Skills
Other Requirements
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Benefits and perks
•Learning Budget
Required skills
SystemVerilog
UVM
ASIC Verification
Coverage Analysis
Debugging
About HCL Technologies
Bangalore
Headquarters